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xicor, inc. 1999 patents pending 9900-5004.9 7/30/99 ww 1 characteristics subject to change without notice 16k X25170 2k x 8 bit spi serial e 2 prom with block lock? protection features ? 5mhz clock rate ? spi modes (0,0 & 1,1) ? 2k x 8 bits 32 byte page mode ? low power cmos <1a standby current <5ma active current ? 2.5v to 5.5v power supply ? block lock protection protect 1/4, 1/2 or all of e 2 prom array ? built-in inadvertent write protection power-up/power-down protection circuitry write enable latch write protect pin ? self-timed write cycle 5ms write cycle time (typical) ? high reliability endurance: 100,000 cycles data retention: 100 years esd protection: 2000v on all pins ? 8-lead pdlp package ? 8-lead soic package ? 14-lead tssop package description the X25170 is a cmos 16384-bit serial e2prom, inter- nally organized as 2k x 8. the X25170 features a serial peripheral interface (spi) and software protocol allowing operation on a simple three-wire bus. the bus signals are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input, allowing any number of devices to share the same bus. the X25170 also features two additional inputs that pro- vide the end user with added ?exibility. by asserting the hold input, the X25170 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. the wp input can be used as a hardwire input to the X25170 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. the X25170 utilizes xicors proprietary direct write? cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. command decode and control logic write control and timing logic write protect logic x decode logic 2k byte array 16 x 256 y decode data register so si sck cs hold wp 16 32 8 32 status register 16 32 x 256 16 x 256 3064 frm f01 direct write ? and block lock ? protection is a trademark of xicor, inc. functional diagram a pplication n ote a v a i l a b l e an61
X25170 2 pin descriptions serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte addresses, and data to be written to the memory are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the serial clock controls the serial bus timing for data input and output. opcodes, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin change after the falling edge of the clock input. chip select (cs ) when cs is high, the X25170 is deselected and the so output pin is at high impedance and unless an internal write operation is underway, the X25170 will be in the standby power mode. cs low enables the X25170, placing it in the active power mode. it should be noted that after power-up, a high to low transition on cs is required prior to the start of any operation. write protect (wp ) when wp is low and the nonvolatile bit wpen is 1, nonvolatile writes to the X25170 status register are dis- abled, but the part otherwise functions normally. when wp is held high, all functions, including nonvolatile writes operate normally. wp going low while cs is still low will interrupt a write to the X25170 status register. if the internal write cycle has already been initiated, wp going low will have no effect on a write. the wp pin function is blocked when the wpen bit in the status register is 0. this allows the user to install the X25170 in a system with wp pin grounded and still be able to write to the status register. the wp pin functions will be enabled when the wpen bit is set 1. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause fea- ture is not used, hold should be held high at all times. tssop nc 1 2 3 4 7 6 5 X25170 v ss nc nc nc nc 8 9 10 11 12 14 13 nc dip/soic v cc hold sck cs 1 2 3 4 6 7 8 X25170 v ss si 5 so wp cs so wp v cc hold sck si 3064 fm fo2.2 pin names 3064 frm t01 symbol description cs chip select input so serial output si serial input sck serial clock input wp write protect input v ss ground v cc supply voltage hold hold input nc no connect pin configuration
X25170 3 principles of operation the X25170 is a 2k x 8 e 2 prom designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. the X25170 contains an 8-bit instruction register. it is accessed via the si input, with data being clocked in on the rising sck. cs must be low and the hold and wp inputs must be high during the entire operation. the wp input is dont care if wpen is set 0. table 1 contains a list of the instructions and their opcodes. all instructions, addresses and data are trans- ferred msb ?rst. data input is sampled on the ?rst rising edge of sck after cs goes low. sck is static, allowing the user to stop the clock and then resume operations. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input to place the X25170 into a pause condition. after releasing hold , the X25170 will resume operation from the point when hold was ?rst asserted. write enable latch the X25170 contains a write enable latch. this latch must be set before a write operation will be completed internally. the wren instruction will set the latch and the wrdi instruction will reset the latch. this latch is auto- matically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle. status register the rdsr instruction provides access to the status reg- ister. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: 3064 frm t02 wpen, bp0 and bp1 are set by the wrsr instruction. wel and wip are read-only and automatically set by other operations. the write-in-process (wip) bit indicates whether the X25170 is busy with a write operation. when set to a 1, a write is in progress, when set to a 0, no write is in progress. during a write, all other bits are set to 1. the write enable latch (wel) bit indicates the status of the write enable latch. when set to a 1, the latch is set, when set to a 0, the latch is reset. the block protect (bp0 and bp1) bits are nonvolatile and allow the user to select one of four levels of protection. the X25170 is divided into four 4096-bit segments. one, two, or all four of the segments may be protected. that is, the user may read the segments but will be unable to alter (write) data within the selected segments. the parti- tioning is controlled as illustrated below. 3064 frm t03 76543210 wpen x x x bl1 bl0 wel wip status register bits array addresses protected bp1 bp0 0 0 none 0 1 $0600C$07ff 1 0 $0400C$07ff 1 1 $0000C$07ff table 1. instruction set 3064 frm t04 *instructions are shown msb in leftmost position. instructions are transferred msb ?rst. instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operations) wrdi 0000 0100 reset the write enable latch (disable write operations) rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address (1 to 32 bytes)
X25170 4 to read the status register the cs line is ?rst pulled low to select the device followed by the 8-bit rdsr instruc- tion. after the rdsr opcode is sent, the contents of the status register are shifted out on the so line. the read status register sequence is illustrated in figure 2. write sequence prior to any attempt to write data into the X25170, the write enable latch must ?rst be set by issuing the wren instruction (see figure 3). cs is ?rst taken low, then the wren instruction is clocked into the X25170. after all eight bits of the instruction are transmitted, cs must then be taken high. if the user continues the write operation without taking cs high after issuing the wren instruction, the write operation will be ignored. to write data to the e 2 prom memory array, the user issues the write instruction, followed by the address and then the data to be written. this is minimally a thirty- two clock operation. cs must go low and remain low for the duration of the operation. the host may continue to write up to 32 bytes of data to the X25170. the only restriction is the 32 bytes must reside on the same page. if the address counter reaches the end of the page and the clock continues, the counter will roll over to the ?rst address of the page and overwrite any data that may have been written. for the write operation (byte or page write) to be com- pleted, cs can only be brought high after bit 0 of data byte n is clocked in. if it is brought high at any other time the write operation will not be completed. refer to figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which cs going high are valid. to write to the status register, the wrsr instruction is fol- lowed by the data to be written. data bits 0, 1, 4, 5 and 6 must be 0. this sequence is shown in figure 6. write-protect enable the write-protect-enable (wpen) bit is available for the X25170 as a nonvolatile enable bit for the wp pin. 3064 frm t05.1 the write protect (wp ) pin and the nonvolatile write pro- tect enable (wpen) bit in the status register control the programmable hardware write protect feature. hardware write protection is enabled when wp pin is low, and the wpen bit is 1. hardware write protection is disabled when either the wp pin is high or the wpen bit is 0. when the chip is hardware write protected, nonvolatile writes are disabled to the status register, including the block protect bits and the wpen bit itself, as well as the block-protected sections in the memory array. only the sections of the memory array that are not block-protected can be written. note: since the wpen bit is write protected, it cannot be changed back to a 0, as long as the wp pin is held low. clock and data timing data input on the si line is latched on the rising edge of sck. data is output on the so line by the falling edge of sck. read sequence when reading from the e 2 prom memory array, cs is ?rst pulled low to select the device. the 8-bit read instruction is transmitted to the X25170, followed by the 16-bit address of which the last 11 are used. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to pro- vide clock pulses. the address is automatically incre- mented to the next higher address after each byte of data is shifted out. when the highest address is reached ($07ff) the address counter rolls over to address $0000 allowing the read cycle to be continued inde?nitely. the read operation is terminated by taking cs high. refer to the read e2prom array operation sequence illustrated in figure 1. wpen wp wel protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable
X25170 5 while the write is in progress following a status register or e 2 prom write sequence, the status register may be read to check the wip bit. during this time the wip bit will be high. hold operation the hold input should be high (at v ih ) under normal operation. if a data transfer is to be interrupted hold can be pulled low to suspend the transfer until it can be resumed. the only restriction is the sck input must be low when hold is ?rst pulled low and sck must also be low when hold is released. the hold input may be tied high either directly to v cc or tied to v cc through a resistor. operational notes the X25170 powers-up in the following state: ? the device is in the low power standby state. ? a high to low transition on cs is required to enter an active state and receive an instruction. ? so pin is high impedance. ? the write enable latch is reset. data protection the following circuitry has been included to prevent in- advertent writes: ? the write enable latch is reset upon power-up. ? a wren instruction must be issued to set the write enable latch. ?cs must come high at the proper clock count in order to start a write cycle. figure 1. read e 2 prom array operation sequence 012 34567 8910 2021222324252627282930 7 65432 10 data out cs sck si so msb high impedance instruction 16 bit address 15 14 13 3 2 1 0 3064 frm f03 figure 2. read status register operation sequence 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction 3064 frm f04
X25170 6 figure 3. write enable latch sequence figure 4. byte write operation sequence 01234567 3064 frm f05 cs si sck high impedance so 012345678910 cs sck si so high impedance instruction 16 bit address data byte 76543210 151413 3210 20 21 22 23 24 25 26 27 28 29 30 31 3064 frm f06
X25170 7 figure 6. write status register operation sequence figure 5. page write operation sequence 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 7654 3210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 data byte n 15 14 13 3210 20 21 22 23 24 25 26 27 28 29 30 31 6543210 3064 frm f07 0123456789 cs sck si so high impedance instruction data byte 76543210 10 11 12 13 14 15 3064 frm f08
X25170 8 absolute maximum ratings* temperature under bias................... C65 c to +135 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to v ss .........................................................C1v to +7v d.c. output current ............................................. 5ma lead temperature (soldering, 10 seconds)...............................300 c d.c. operating characteristics (over the recommended operating conditions unless otherwise speci?ed.) 3064 frm t08.3 power-up timing 3064 frm t09 capacitance t a = +25 c, f = 1mhz, v cc = 5v 3064 frm t10.1 notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. (3) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter limits units test conditions min. max. i cc v cc supply current (active) 5ma sck = v cc x 0.1/v cc x 0.9 @ so = open, cs = v ss i sb v cc supply current (stand- 1 m a cs = v cc , v in = v ss or v cc i li input leakage current 10 m a v in = v ss to v cc i lo output leakage current 10 m a v out = v ss to v cc v il (1) input low voltage C1 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v v cc = 5v, i ol = 3ma v oh1 output high voltage v cc C0.8 v v cc = 5v, i oh = -1.6ma v ol2 output low voltage 0.4 v v cc = 2.70v, i ol = 1.5ma v oh2 output high voltage v cc C0.3 v v cc = 2.70v, i oh = -0.4ma symbol parameter min. max. units t pur (3) power-up to read operation 1ms t puw (3) power-up to write operation 1ms symbol parameter max. units test conditions c out (2) output capacitance (so) 8pf v out = 0v c in (2) input capacitance (sck, si, cs , wp , hold ) 6pf v in = 0v recommended operating conditions 3064 frm t06.1 temperature min. max. commercial 0 c +70 c industrial C40 c +85 c military C55 c +125 c 3064 frm t07.1 supply voltage limits X25170 5v 10% X25170-2.5 2.5v to 5.5v *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability.
X25170 9 a.c. characteristics (over recommended operationg conditions, unless otherwise specified) data input timing 3064 frm t12.2 data output timing 3064 frm t13.2 notes: (4) this parameter is periodically sampled and not 100% tested. (5) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle symbol parameter min. max. units f sck clock frequency 0 5 mhz t cyc cycle time 200 ns t lead cs lead time 100 ns t lag cs lag time 100 ns t wh clock high time 80 ns t wl clock low time 80 ns t su data setup time 20 ns t h data hold time 20 ns t ri (4) data in rise time 2 m s t fi (4) data in fall time 2 m s t hd hold setup time 40 ns t cd hold hold time 40 ns t cs cs deselect time 100 ns t wc (5) write cycle time 10 ms symbol parameter min. max. units f sck clock frequency 0 5 mhz t dis output disable time 100 ns t v output valid from clock low 80 ns t ho output hold time 0ns t ro (4) output rise time 50 ns t fo (4) output fall time 50 ns t lz (4) hold high to output in low z 50 ns t hz (4) hold low to output in high z 50 ns a.c. conditions of test 7037 frm t11 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and outputtiming levels v cc x 0.5 equivalent a.c. load circuit output 3064 frm f09.1 5v 1.44k w 1.95k w 100pf output 3v 1.64k w 4.63k w 100pf
X25170 10 serial output timing sck cs so si msb out msbC1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis 3064 frm f10.1 t lag serial input timing sck cs si so msb in t su t ri t lag 3064 frm f11 t lead t h lsb in t cs t fi high impedance
X25170 11 hold timing sck cs si so t hd 3064 frm f12.1 t lz hold t hz t cd t hd t cd symbol table must be steady will be steady may change from low will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance waveform inputs outputs
X25170 12 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ . 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62) 3926 frm f01
X25170 13 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 C 8 x 45 8-lead plastic small outline gull wing package type s 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint note: all dimensions in inches (in parentheses in millimeters) 3926 frm f22.1
X25170 14 packaging information note: all dimensions in inches (in p arentheses in millimeters) 14-lead plastic, tssop package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 C 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) 3926 frm f32
X25170 15 ordering information part mark convention X25170 p-v device v cc limits blank = 5v 10% temperature range blank = commercial = 0 c to +70 c package limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?cation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the f reedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?tness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?cations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874 , 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) su pport or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. s8 = 8-lead soic t 2.5 = 2.5v to 5.5v m = military = C55 c to +125 c p8 = 8-lead plastic dip v14 = 14-lead tssop i = industrial = C40 c to +85 c x blank = 8-lead soic v = 14-lead tssop p = 8-lead plastic dip x blank = 5v 10%, 0c to +70c f = 2.5v to 5.5v, 0c to +70c i = 5v 10%, C40c to +85c g = 2.5v to 5.5v, C40c to +85c X25170

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